In semiconductor fabrication, a plurality of individual structures are produced on a substrate (generally a semiconductor substrate). Etching methods, polishing methods, deposition methods and the like are used for this purpose. For many structure elements such as, for example, electrical terminal contacts, vertically contact-connecting contact hole fillings (vias), interconnects, etc., it is necessary firstly to etch trenches. Such trenches can be arranged in the semiconductor substrate, in a layer, for example, a dielectric layer, arranged on or above the semiconductor substrate, or in some other region of a semiconductor product. When the trenches are subsequently filled, usually a filling material is deposited over the whole area onto the partly finished semiconductor product and then removed superficially as far as the level of the upper edge of the trench. A partial etching back, a chemical mechanical polishing operation or some other etching method can be used for this purpose.
In semiconductor fabrication, it is always desirable for the semiconductor product to have a surface that is as planar as possible, i.e., a surface whose topmost structures produce the least possible topographies or height differences. This is necessary particularly owing to the limited depth of focus in the lithographic patterning of masks for further processing steps. A relatively planar surface is achieved by chemical mechanical polishing, for example, which involves moving a polishing pad in a lateral direction parallel to the substrate surface or to the surface of the semiconductor product, wherein a polishing slurry containing an etching component and also polishing grains that cause mechanical abrasion covers the polished surface and the polishing pad.
However, the plane surface ideally sought by means of the chemical mechanical polishing is generally achieved only approximately; different high removal rates of structure elements composed of different materials on different positions of a wafer (or within the circuit of a single chip) lead to height fluctuations of the top side which have an effect locally and globally over the entire wafer surface. These thickness fluctuations arise on account of the polishing process itself. The fluctuations turn out to be greater, the thicker a layer was that was removed beforehand by chemical mechanical polishing, the lower the selectivity is during the etching of a layer with respect to an underlying layer, and the longer the polishing operation lasts. A long polishing time is attained, in particular, when materials that are difficult to polish are to be removed. Thus, by way of example, time durations of a polishing operation carried out of 1000 seconds or more can lead to topographies that make it more difficult to further process the only partly finished semiconductor product.
If a trench is filled with a filling material, then the latter simultaneously covers the surface of the semiconductor product laterally outside the trench (and also above the trench itself) and must subsequently be removed again from the semiconductor product over the whole area at least at the level above the top side of the trench. It is typically etched back as far as a previously deposited etching stop layer that is more difficult to polish than the filling material. The etching stop layer can also comprise a layer sequence, particularly if further requirements are to be taken into account in the production of an integrated circuit. The layer sequence can comprise, for example, diffusion barrier layers, layers having a high electrical conductivity, adhesion-enhancing layers or other layers. If such layers were deposited below the actual filling material into the trench and the surface of the semiconductor product, these layers must subsequently be removed again from the surface of the semiconductor product outside the trench. Further polishing operations with in part further polishing slurries can be used for this purpose.
The polishing of the trench-filling material above the trench can already give rise to the above-mentioned unevennesses over the wafer area or the area of the semiconductor product. During the subsequent removal of the layers that were deposited below the trench filling and still cover the surface outside the trench, the unevennesses can also be intensified. By way of example, tungsten-containing layers or layer sequences can lead to additional considerable topographies, for instance if they are removed with the aid of a low polishing rate during a relatively lengthy polishing step. However, with other materials, too, there is the problem that with the aid of chemical mechanical polishing operations that are usually carried out after the filling of trenches or other depressions in order to remove excess material, the polished surface subsequently has a poorer planarity, i.e., greater unevennesses.